Cost-Reduced LoRa Sensor PCB Redesign

About the project

SCOPE - 75 components, 47 nets, 240 connections. Single PCB, 4-layer (2 signal + solid GND + power), all SMD, one-sided placement preferred for JLCPCB assembly cost. - Board outline: <<FILL IN>> mm, 4x M3 mounting holes, connectors on specified edges. - Blocks: CN3163 solar Li-ion charger / DW01A+8205A cell protection / INA219 with 0R1 1206 shunt / TPS63802 buck-boost to 3V3 / two AO3401A gated rails / USB-C 2.0 with USBLC6 ESD / RYLR998 LoRa module / TTP223 capacitive touch pad / JST sensor headers. LAYOUT CONSTRAINTS (non-negotiable, these are why the job needs a real engineer) 1. TPS63802: inductor + input/output caps in the tightest possible loop, switch node copper minimised, solid ground return directly beneath. 2. The GPIO0 ADC divider (220k/68k) and the IPEX antenna line must be kept away from that switch node. 3. INA219 to the 0R1 shunt must be a true Kelvin/4-wire sense off the pad inner edges. 4. ESP32-C3-MINI-1U: antenna end overhangs the board edge, keepout on all layers, all 22 GND pads stitched to the pour. 5. USB D+/D- as a matched differential pair; USBLC6 within 5 mm of the connector, in series with the pair (not stubbed). 6. Touch IC within ~10 mm of its copper pad; thin, isolated trace. 7. Board must measure <=40 uA in sleep — no leakage paths between the gated rails. DELIVERABLES - Native source project (EasyEDA Pro preferred, KiCad 8 accepted) — source files are part of the deliverable, not just outputs. - Gerbers + drill, JLCPCB-format BOM and CPL/pick-and-place. - 3D render + top/bottom assembly drawing. - Impedance/stackup note for the 4-layer JLC stackup used. ACCEPTANCE (objective, not subjective) - DRC clean at JLCPCB 4-layer capability. - Your exported netlist must diff EXACTLY against the netlist I supply (240 connections). I check this with a script — no manual argument needed. - JLCPCB's online DFM/assembly checker passes with zero errors. - Two rounds of revisions after my Gerber review are included in the price. WHAT I SUPPLY ON DAY 1 - Full schematic (PDF, 9 annotated blocks), complete netlist, BOM with LCSC part numbers, assembly/test checklist, mechanical outline. ANSWER THESE IN YOUR BID (bids without answers are ignored) 1. Where do you place the inductor loop relative to the IC and the ground plane on a TPS63802-class buck-boost, and why? 2. How do you connect a current-sense amplifier to a 1206 shunt? 3. Name two JLCPCB-specific choices that reduce assembly cost on a board like this. 4. Link one board YOU laid out that has a switching regulator AND an RF module. Please do not send template proposals. I will shortlist 2-3 people and pay a small fixed fee for a placement-only sketch before awarding the full project. Replace <<FILL IN>> before posting — nobody can bid honestly without the outline. Your locked TX form factor is a 110 × 80 × 35 mm enclosure around a 99 × 69 mm panel, so ~95 × 65 mm with the USB-C and JST edges called out is the sane default.

Skills required