ESP32 Hardware & PCB Design Optimization, LTspice/ANSYS Thermal Simulation & Production PCB Package

About the project

4-Layer ESP32 Hardware Optimization, LTspice/ANSYS Thermal Simulation & Production PCB Package IMPORTANT: NO PLACEHOLDER BIDS. Proposals starting with generic templates or placeholder quotes will be immediately declined and reported. To prove you have read and understood the entire project scope, your proposal MUST start with the exact phrase: HARDWARE-EXPERT Project Overview: We are seeking an expert Senior Embedded Hardware / PCB Design Engineer to finalize, simulate, optimize, and release a high-reliability, 4-layer ESP32-based industrial electronic system. This project demands strict adherence to engineering standards, component lifecycle management, galvanic isolation, and rigorous CAD validation. Zero ERC/DRC errors in KiCad are mandatory. Scope of Work & Deliverables Milestone 1: Schematic Optimization & Electrical Simulation: LTspice PDN & Circuit Simulation: Perform transient load, startup analysis, and simulate power delivery stability between the HLK Network module, secondary power modules, and ESP32-S3. Schematic Audit & Protection: Integrate WM8960 codec. Implement robust hardware protection (OVP, TVS diodes, fuses, surge protection). Safety & Isolation: Establish a Galvanic Isolation strategy with defined Creepage & Clearance limits between high-power AC/DC lines and RF/logic circuits. M1 Deliverables: Native editable KiCad schematic source files, custom component libraries, structured BOM with MPNs (active production components only), clean ERC Report with ZERO critical errors/floating pins, LTspice .asc simulation profiles/waveforms, and Isolation Design Note. Milestone 2: 4-Layer PCB Layout, ANSYS Thermal Simulation & Manufacturing Release PCB Design & Layer Separation: Multi-layer PCB layout optimizing RF stability, grounding, DFM/DFA, and strict physical separation of AC/DC tracks from low-voltage RF/ESP32 logic. Thermal & Reliability Simulation: Conduct full 3D Thermal Simulation via ANSYS Icepak under continuous 24/7 load across extreme ambient conditions (-10°C to +65°C, up to 95% RH). Implement proper thermal mitigation (vias, copper pours, heatsinks) to validate a 5+ year operational lifespan based on Arrhenius derating analysis. Interfaces & Test Points: Integrate ICT test points for all critical rails and auto-reset UART/USB flashing circuitry. M2 Deliverables: Final native KiCad PCB source files & Stackup definition. Clean DRC Report with ZERO errors. ANSYS Icepak native simulation package, high-res video demo, and PDF Thermal Analysis Report. Reliability Derating Report & 3D STEP mechanical model. Complete Manufacturing Package: Gerbers, ODB++, IPC-D-356 Netlist, Pick & Place (Centroid), Assembly Drawings, Fabrication Notes, Stencil files, and complete BOM (including antennas: 2x **************). Signed Manufacturing Release Checklist, GPIO Mapping Sheet, and Test Strategy document, and any final project-required document.

Skills required